GS4901B/GS4900B Preliminary Data Sheet
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
H_Start_3
61h
15-0
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER3_H.
R/W
0
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_3.
Reference: Section 3.8.3 on page 59
H_Stop_3
62h
15-0
The value programmed in this register indicates the
pixel end point for the trailing edge of the
R/W
0
user-programmed H Sync signal USER3_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference: Section 3.8.3 on page 59
V_Start_3
63h
63h
15
Reserved. Set this bit to zero when writing to 63h.
–
–
0
14-0
The value programmed in this register indicates the start R/W
line number of the leading edge of the
user-programmed V Sync signal USER3_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_3.
Reference: Section 3.8.3 on page 59
V_Stop_3
64h
64h
15
Reserved. Set this bit to zero when writing to 64h.
–
–
0
14-0
The value programmed in this register indicates the end R/W
line number of the trailing edge of the user-programmed
V Sync signal USER3_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference: Section 3.8.3 on page 59
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