GS9004C CABLE EQUALIZER - DETAILED DEVICE DESCRIPTION
The GS9004C Cable Equalizer is a bipolar integrated circuit
used to equalize SMPTE 259M signals from a co-axial cable.
The device is implemented as a fourteen pin SOIC, powered
from a single five volt supply. With an operating frequency up
to 400 Mb/s, the equalizer consumes about 285 mW of
power.
The Serial Digital signal is connected to the input (pins 8, 9)
either differentially or single ended with the unused input
being decoupled. The equalized signal is generated by
passing the cable signal through a voltage variable filter
having a characteristic which closely matches the inverse
cable loss characteristic. Additionally, the variation of the filter
characteristic with control voltage is designed to imitate the
variation of the inverse cable loss characteristic as the cable
length is varied.
The amplitude of the equalized signal is monitored by a peak
detector circuit which produces an output current with a
polarity corresponding to the difference between the desired peak
signal level and the actual peak signal level.
+5V
10µ
+
1.0
150
GND
68
1.8p
This output is integrated by an external AGC filter capacitor
(AGC CAP pin 7), providing a steady control voltage for the
voltage variable filter.
A separate signal strength indicator output, (SSI pin 6),
proportional to the amount of AGC, is also provided. As the
filter characteristic is varied automatically by the application of
negative feedback, the amplitude of the equalized signal is
kept at a constant level which is representative of the original
amplitude at the transmitter.
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
output signal having pseudo-ECL voltage levels. These outputs,
DATA and DATA, are available from pins 13 and 14 respectively.
An OUTPUT 'EYE' MONITOR (pin 3) allows verification of
signal integrity after equalization, prior to reslicing.
68
V
CC
SDO4
SDO3
1.0
100
5
6
100
100n
1.8p
GND
SI
SI
VCC
SO2 4
SO2 3
SO1 2
SO1 1
150
68
7
100n
8
SDO2
1.0
150
68
1.8p
100n
1
V
CC
V
CC
50
V
CC
V
CC
100n
100n
OEM
+
V
CC
SSI
10
100n
100n
2
3
4
5
6
7
V
CC
V
CC
OEM
V
CC
N/C
SSI
AGC
DATA
DATA
GND1
GND
GND
IN -
IN+
14
13
12
11
680
V
CC
GS9007
680
OEM
SDO1
1.0
1.8p
150
10
9
8
47p
75
75
SDI
18n
47p
113
GS9004C
All resistors in ohms, all capacitors in microfarads,
all inductors in henries unless otherwise stated.
Fig. 1 Test Circuit
8281 CABLE
CABLE
DRIVER
DATA
CABLE
DRIVER
ANRITSU
ME522A
OR
TEKTRONIX
TSG422
D.U.T.
VERTICAL
IN
CLOCK
OSCILLOSCOPE
TRIGGER
IN
Fig. 2 Test Set-up 1
3
521 - 72 - 00
GENNUM [ GENNUM CORPORATION ]
