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GS9020ACTVE3 参数 Datasheet PDF下载

GS9020ACTVE3图片预览
型号: GS9020ACTVE3
PDF下载: 下载PDF文件 查看货源
内容描述: GENLINX -TM II GS9020A串行数字视频输入处理器 [GENLINX -TM II GS9020A Serial Digital Video Input Processor]
分类和应用: 消费电路商用集成电路
文件页数/大小: 31 页 / 403 K
品牌: GENNUM [ GENNUM CORPORATION ]
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PIN CONNECTIONS
ANC_DATA
TRS_ERR
CLIP_TRS
ANC_CHKSM
BLANK_EN
SDOMODE
BYPASS_EDH
VBLANKS/L
SGND
SDO
SDO
SVDD
VDD
GND
FLAG_MAP
F2
F1
F0
H
V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
GS9020A
10
51
TOP VIEW
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
SCL/P4
SDA/P3
A2/P2
A1/P1
A0/P0
R/W
A/D
CS
VDD
GND
RESET
STD3
STD2
STD1
STD0
FL4
FL3
FL2
FL1
FL0
GS9020A
VDD
GND
GND
VDD
VDD
SDI
SDI
SDI
VDD
SDI
VDD
SCI
SCI
SCI
VDD
SCI
VDD
GND
HOSTIF_MODE
FIFOE/S
CRC_MODE
P7
P6
P5
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
VDD
GND
DOUT0
PCLKOUT
FIFO_RESET
NO_EDH
FLYWDIS
INTERRUPT
F_R/W
S0
S1
PIN DESCRIPTIONS
NUMBER
6, 7
10, 11
15
SYMBOL
SDI, SDI
SCI, SCI
HOSTIF_MODE
TYPE
I
I
I
Differential serial data inputs.
Differential serial clock inputs.
Host interface mode select. When HIGH, the host interface is configured for I²C mode. When
LOW, the host interface is configured for parallel port mode.
FIFO_RESET pulse control. When HIGH, the output FIFO_RESET pulse occurs on the EAV
word. When LOW, the output FIFO_RESET pulse occurs on the SAV word.
CRC_MODE enable. When HIGH, CRC_MODE is enabled. When LOW, CRC_MODE is
disabled.
In parallel port mode, these are bits 7:5 of the host interface address/data bus. In I²C mode,
these pins must be set LOW.
In parallel port mode, this is bit 4 of the host interface address/data bus. In I²C mode, this is the
serial clock input for the I²C port.
In parallel port mode, this is bit 3 of the host interface address/data bus. In I²C mode, this is the
serial data pin for the I²C port.
In parallel port mode, these are bits 2:0 of the host interface address/data bus. In I²C mode,
these are input bits which define the I²C slave address for the device.
Parallel port read/write control. When HIGH, the parallel port is configured as an output (read
mode). When LOW, the parallel port is configured as an input (write mode). In I²C mode, this
pin must be set HIGH.
DESCRIPTION
16
FIFOE/S
I
17
CRC_MODE
I
18 - 20
P[7:5]
I/O
21
SCL/P4
I/O
22
SDA/P3
I/O
23 - 25
A[2:0]/P[2:0]
I/O
26
R/W
I
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