Write Mode, F_R/W = 0
The first time the device samples the F_R/W LOW (at t0) it is
instructed to stop driving the FL[4:0] pins. On each
subsequent rising clock edge (and F_R/W LOW) the device
latches in the data present on S[1:0] and FL[4:0] (at t1, t2, t3
and t4). In this example, the S[1:0] pins begin at "00" and
are incremented each clock cycle to update all the error
flags, validity bits, and the IN/OUT control bit. Note that if a
write cycle is performed to update, say the FF error flags
(S[1:0] = 00), only the FF flags are updated, and the others
are unaffected.
S[1:0]
00
FL4
FL3
FL2
FL1
FL0
FF UES
AP UES
FF IDA
AP IDA
FF IDH
AP IDH
FF EDA
AP EDA
FF EDH
AP EDH
01
10
ANC
UES
ANC
IDA
ANC
IDH
ANC
EDA
ANC
EDH
11
IN/OUT
APV
FFV
0
0
A delay time, tFDIS, is necessary to change the FL[4:0] pins
from output mode to input mode as defined in the AC timing
table (See Fig.5b). The external controller can begin to
drive the FL[4:0] bus after this delay time. A simple way to
allow for this is to wait one clock cycle before starting to
drive the FL[4:0] port and thus prevent bus contention (but
set the S[1:0] inputs when F_R/W goes LOW so the flags
are not unintentionally affected).
The IN/OUT bit has no effect on writes to the error flags. IN/
OUT is a control bit used to determine if the flags read from
the flag port during flag port read cycles represent
incoming or outgoing EDH flags. If this bit is set HIGH, all
subsequent reads are from the incoming EDH packet. If this
bit is set LOW, then all subsequent reads are from the
updated outgoing packet. When the IN/OUT bit is written to,
the value remains latched until it is reprogrammed. The IN/
OUT bit is set LOW upon reset of the chip.
At t5, the F_R/W pin is sampled HIGH, indicating a read
operation. Also at this time, the device reads in the
information on the S[1:0] pins. Upon sampling a read
operation, the device will begin driving the FLAG PORT
after a delay, tFEN, (see Fig. 5c), with invalid data. The
requested information is output on the FL[4:0] pins on the
subsequent clock, t6, plus an output delay time, (see AC
timing table and Fig. 2). That is, there is a one clock latency
between sampling of the S[1:0] pins and when the
corresponding output information is presented on the
FL[4:0] pins. In this example, the S[1:0] pins begin at "00"
and are incremented each clock cycle to read all the error
flags, EDH_CHKSM, validity, and S bits.
3.9.2 Read Mode
When the F_R/W pin is HIGH, the flag port is in read mode
and the FL[4:0] pins are configured as outputs. The data
present on the FL[4:0] output pins, as controlled by the
S[1:0] pins, is summarized below.
Read Mode, F_R/W = 1
S[1:0]
00
FL4
FL3
FL2
FL1
FL0
FF UES
AP UES
ANC UES
FF IDA
AP IDA
FF IDH
AP IDH
FF EDA
AP EDA
FF EDH
AP EDH
01
10
ANC
IDA
ANC
IDH
ANC
EDA
ANC
EDH
The FLAG PORT is synchronous to the clock pin (PCLKIN)
and hence adequate setup and hold times must be
provided as indicated in the AC timing information and Fig.
1. FLAG PORT read/write cycles, relative to the data stream,
should take place as outlined in section 5.3 (HOST
INTERFACE READ/WRITE TIMING)
11
EDH_
APV
FFV
S
CHKSUM
Note that the 15 error flags can be read from the incoming
or outgoing EDH packet (see IN/OUT control bit above).
However, the EDH_CHKSM flag available on pin FL4 when
S[1:0] = 11 is only valid if IN/OUT is LOW. Also, the APV
and FFV bits available on pins FL[3:2] when S[1:0] = 11 are
only valid when IN/OUT is HIGH (that is, the validity bits are
always read from the incoming EDH packet). The S bit is
available regardless of the state of the IN/OUT bit.
3.10 CRC_MODE and FLAG_MAP Mode
PIN
LOGIC OPR
HOST BIT
CRC_MODE
FLAG_MAP
OR
FLAG_MAP
3.9.3 Flag Port READ/WRITE Timing
A common configuration is to have an input EDH chip that
checks for errors at the input of a piece of equipment,
followed by a processing block that manipulates the data,
followed by an output EDH chip that updates the CRC
values in the EDH packet before the data exits the
equipment. Because the processing block changes the
data values, the CRC values in the EDH packet no longer
represent the data stream. The output EDH chip updates
Figure 5a shows a FLAG PORT write cycle followed by a
FLAG PORT read cycle and illustrates the read/write timing
requirements.
A write cycle is initiated by changing the F_R/W signal from
HIGH to LOW.
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