1. OUTPUT HIGH Z
A HIGH Z pin allows the data outputs to be put into a high
impedance state which disconnects them from the output
traces. This feature is ideal for input expansion in router
applications as it eliminates the need for input muxes or
crosspoints.
2. SIGNAL STRENGTH INDICATION/CARRIER DETECT
GS9024C
The GS9024C incorporates an analog signal strength
indicator/carrier detect output (SSI/CD) which indicates
both the presence of a carrier and the amount of
equalization applied to the signal. The voltage output of this
pin versus cable length (signal strength) is shown in
Figure 10. With 0m of cable (800mV input signal levels), the
SSI/CD output voltage is approximately 4.5V.
As the cable length increases, the SSI/CD voltage
decreases linearly providing accurate correlation between
the SSI/CD voltage and cable length.
Fig. 9 Output Data Waveform at 270Mb/s, 300m
DETAILED DESCRIPTION
The GS9024C Automatic Cable Equalizer is a bipolar
integrated circuit designed to equalize serial digital data
signals between 30Mbps and 360Mbps. Powered from a
single +5V or -5V supply, the device consumes
approximately 240mW of power.
The serial data signal is connected to the input pins
(SDI/SDI) either differentially or single ended. The input
signal passes through a variable gain equalizing stage
whose frequency response closely matches the inverse
cable loss characteristic. In addition, the variation of the
frequency response with control voltage imitates the
variation of the inverse cable loss characteristic with cable
length. The gain stage provides up to 40dB of gain at
200MHz which will typically result in equalization of greater
than 350m at 270Mb/s of Belden 8281 cable.
The edge energy of the equalized signal is monitored by a
detector circuit which produces an error signal
corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is
integrated by an external differential AGC filter capacitor
(AGC+/AGC-) providing a steady control voltage for the
gain stage. As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is kept
at a constant level which is representative of the original
edge energy at the transmitter.
The equalized signal is DC restored, thereby restoring its
logic threshold to its corrective level regardless of shifts due
to AC coupling. The digital output signals have PECL
voltage levels (800mV) and are available at pins SDO and
SDO.
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GENNUM CORPORATION
When the signal strength decreases to the level set at the
"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage
goes to a logic "0" state (0.8V) and can be used to drive
other TTL/CMOS compatible logic inputs. In addition, when
loss of carrier is detected the SDO/SDO outputs are muted
(set to a known static state).
5
SSI/CD OUTPUT VOLTAGE (V)
4
3
CD_ADJ
CONTROL RANGE
2
1
0
0
50
100
150
200
250
300
350
400
450
500
CABLE LENGTH (m)
Fig. 10
3. CARRIER DETECT THRESHOLD ADJUST
The threshold level at which loss of carrier is detected is
adjustable via external resistors at the CD_ADJ pin. The
control voltage at the CD_ADJ pin is set by a simple resistor
divider circuit. The threshold level is adjustable from 200m
to 350m. By default (no external resistors), the threshold is
typically 320m. Connecting this pin to Ground disables the
SDO/SDO muting function and allows for maximum
possible cable length equalization.
This feature is designed for use in applications such as
routers where signal crosstalk and circuit noise cause the
equalizer to output erroneous data when no input signal is
present. This problem is not solved by using a
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GENNUM [ GENNUM CORPORATION ]
