GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Key Features
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SMPTE 259M-C compliant descrambling and NRZI to
NRZ decoding (with bypass)
DVB-ASI 8b/10b decoding
Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
extraction and clock rate interchange, and ancillary
data packet extraction
Integrated VCO and reclocker
User selectable additional processing features
including:
TRS, ANC data checksum, and EDH CRC error
detection and correction
programmable ANC data detection
illegal code remapping
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Internal flywheel for noise immune H, V, F extraction
Automatic standards detection and indication
Enhanced Gennum Serial Peripheral Interface (GSPI)
JTAG test interface
Polarity insensitive for DVB-ASI and SMPTE signals
+1.8V core power supply with optional +1.8V or +3.3V
I/O power supply
Small footprint (8mm x 8mm)
Low power operation (typically 145mW)
Pb-free
Description
The GS9090B is a 270Mb/s reclocking deserializer with an
internal FIFO. It provides a complete receive solution for
SD-SDI and DVB-ASI applications.
In addition to reclocking and deserializing the input data
stream, the GS9090B performs NRZI-to-NRZ decoding, de-
scrambling as per SMPTE 259M-C, and word alignment
when operating in SMPTE mode. When operating in
DVB-ASI mode, the device will word align the data to K28.5
sync characters and 8b/10b decode the received stream.
The internal reclocker features a very wide input jitter tol-
erance, and is fully compatible with both SMPTE and
DVB-ASI input streams.
The GS9090B includes a range of data processing
functions such as EDH support (error detection and han-
dling), and automatic standards detection. The device can
also detect and extract SMPTE 352M
payload identifier packets and independently identify the
received video standard. This information is read from in-
ternal registers via the host interface port.
The GS9090B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to car-
ry out tasks such as data alignment / delay, clock phase in-
terchange, MPEG packet extraction and clock rate
interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed
format, with the associated parallel clock output signal op-
erating at 27MHz.
The device may also be used in a low-latency data pass
through mode where only descrambling and word align-
ment will be performed in SMPTE mode.
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Applications
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SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
GS9090B GenLINX® III 270Mb/s Deserializer for SDI
Data Sheet
40749 - 5
May 2010
1 of 72
GENNUM [ GENNUM CORPORATION ]
