G570SA 参数 Datasheet PDF下载

Global Mixed-mode Technology Inc.

Parameter Measurement Information

V

PP

C

L

V

CC

C

L

G570

LOAD CIRCUIT

50%

LATCH

t

off

t

on

V

O(xVPP)

90%

10%

LOAD CIRCUIT

V

DD

50%

GND

LATCH

t

off

V

I(12V)

V

O(xVCC)

GND

t

on

90%

10%

GND

V

I(5V)

GND

V

DD

VOLTAGE WAVEFORMS

VOLTAGE WAVEFORMS

Figure 1. Test Circuits and Voltage Waveforms

Table of Timing Diagrams

DATA

D8

D7

D6

D5

D4

D3

D2

D1

D0

LATCH

CLOCK

Note:Data is clocked in on the positive leading edge of the clock. The latch should occur before the next

positive leading edge of the clock. For definition of D0 to D8, see the control logic table.

Figure 2. Serial-Interface Timing

Ver 1.0

Nov 09, 2000

TEL: 886-3-5788833

http://www.gmt.com.tw

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