G574_06 参数 Datasheet PDF下载

Global Mixed-mode Technology Inc.

G574

D2

D1

D0

Latch Delay Time

DATA

D10

D9

D8

D7

D6

D5

D4

D3

Data Setup Time

Data Hold Time

LATCH

Clock Delay Time

CLOCK

Note:Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next

positive edge of the clock. For definition of D0 to D10, see the control logic table.

Figure 2. Serial-Interface Timing for Independent xVPP Switching When MODE=5V or 3.3V

DATA

D8

D7

D6

D5

D4

D3

D2

D1

D0

Data Setup Time

Data Hold Time

Latch Delay Time

LATCH

Clock Delay Time

CLOCK

Note:Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next

positive edge of the clock. For definition of D0 to D8, see the control logic table.

Figure 3. Serial-Interface Timing When MODE = 0V or Floating

Ver: 1.2

Jul 28, 2006

TEL: 886-3-5788833

http://www.gmt.com.tw

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