Global Mixed-mode Technology Inc.
Pin Description
PIN
1
2.3
4
5
G698/G699
NAME
CD
GND
RESET
(G698L/G699L)
FUNCTION
External Programmable time delay is set by the capacitor connect to C
D
pin.
Ground
RESET
Output remains low while V
CC
is below the reset threshold, and for delay time set by C
D
after V
CC
rises above the reset threshold.
RESET Output remains high while V
CC
is below the reset threshold, and for delay time set by
C
D
after V
CC
rises above the reset threshold.
RESET (G698H)
VCC
Supply Voltage (+5V, +3.3V, +3.0V)
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a
known state. The G699L/G698L/G698H assert reset to
prevent code-execution errors during power-up,
power-down, or brownout conditions. They assert a
reset signal whenever the V
CC
supply voltage declines
below a preset threshold (V
TH-
), keeping it asserted for
time delay set by capacitor connected to C
D
pin, after
V
CC
has risen above the high reset threshold V
TH+
(V
TH-
+V
HYS
). The G699L uses an open-drain output,
and the G698L/G698H have a push-pull output stage.
Connect a pull-up resistor on the G699L’s RESET out-
put to any supply between 0 and 5.5V.
The time delay is set by external capacitor C
D
, and
internal pull up current I
CD
. When the voltage at C
D
pin exceeds the buffer threshold, typically 1.25V, the
RESET output high (RESET output low). The volt-
age detector and buffer have built-in hysterisis to
prevent erratic reset operation. The formula of time
delay is T (ms)
≅
1685 C
D
(µF). Fig1 and Fig2 show a
timing deagram and a Functional Block.
Ensuring a Valid Reset Output Down to V
CC
= 0
When V
CC
falls below 0.8V, the G698 RESET output
no longer sinks current—it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to RESET can drift to undetermined voltages.
This presents no problem in most applications since
most µP and other circuitry is inoperative with
VCC
below 0.8V. However, in applications where RESET
must be valid down to 0V, adding a pull-down resistor
to RESET causes any stray leakage currents to flow
to ground, holding RESET low (Figure 3). R1’s value
is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground.
A 100kΩ pull-up resistor to V
CC
is also recommended
for the G699L if RESET is required to remain valid
for V
CC
< 0.8V.
VCC
G698
RESET
GND
R1
100k
Figure3.
RESET
Valid to V
CC
= Ground Circuit
Ver: 1.3
Jun 03, 2004
TEL: 886-3-5788833
http://www.gmt.com.tw
6
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
