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GS71024GT-10 参数 Datasheet PDF下载

GS71024GT-10图片预览
型号: GS71024GT-10
PDF下载: 下载PDF文件 查看货源
内容描述: 64K ×24的1.5Mb异步SRAM [64K x 24 1.5Mb Asynchronous SRAM]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 279 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS71024T/U
TQFP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 8, 9, 10, 12, 15 ns
• CMOS low power operation: 190/170/160/130/110 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
GT: Pb-Free 100-pin TQFP available
64K x 24
1.5Mb Asynchronous SRAM
1
A
B
C
D
E
F
G
H
2
3
4
8, 9, 10, 12, 15 ns
3.3 V V
DD
Center V
DD
and V
SS
Fine Pitch BGA Bump Configuration
5
6
DQ
DQ
DQ
V
SS
V
DD
DQ
DQ
DQ
A
3
DQ
DQ
DQ
DQ
DQ
DQ
A
15
A
2
CE2
CE1
A
5
A
7
A
9
A
11
A
14
A
1
WE
OE
A
4
A
6
A
8
A
10
A
13
A
0
DQ
DQ
DQ
DQ
DQ
DQ
A
12
DQ
DQ
DQ
V
DD
V
SS
DQ
DQ
DQ
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Pin Descriptions
Symbol
A
0
to A
15
X/Y
WE
CE1, CE2
V
DD
Description
Address input
Vector Input
Write enable input
Chip enable input
+3.3 V power supply
Symbol
DQ
1
to DQ
24
V/S
OE
V
SS
Description
Data input/output
Address Multiplexer Control
Output enable input
Ground
Block Diagram
A0
Row
Decoder
Address
Input
A14
A15
X/Y
V/S
CE1
CE2
WE
OE
Memory Array
1024 x 1536
0
1
Q
Column
Decoder
Control
I/O Buffer
DQ1
DQ24
Rev: 1.05 11/2004
1/13
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.