GS71024T/U
Write Cycle 1: WE control
t
WC
Address
OE
t
t
WR
AW
t
t
CW
(*1)
CE1
VW
t
VS
V/S
WE
t
t
WP
AS
(*2)
t
t
DH
DW
Data valid
Data In
t
t
WLZ
WHZ
Data Out
High impedance
(*3)
*1 CE1 represents both CE1 low and CE2 high.
(*3)
*2 Write is executed when both CE1 and WE are at low simultaneously.
*3 Do not apply the data input voltage to the output while DQ pin is in output condition.
Write Cycle 2: CE control
t
WC
Address
OE
t
t
WR1
AW
t
t
t
AS
CW
VW
(*1)
CE1
V/S
WE
t
WP
t
t
DH
DW
Data valid
Data In
Data Out
High impedance
*1 CE1 represents both CE1 low and CE2 high.
Rev: 1.05 11/2004
9/13
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
