GS81032AT/Q-150/138/133/117/100/66
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Pin Name State
LBO
FT
ZZ
L
H or NC
L
H or NC
L or NC
H
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
I
nterleaved Burst Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Byte Write Truth Table
Function
Read
Read
Write byte
A
Write byte
B
Write byte
C
Write byte
D
Write all bytes
Write all bytes
GW
H
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
L
X
B
A
X
H
L
H
H
H
L
X
B
B
X
H
H
L
H
H
L
X
B
C
X
H
H
H
L
H
L
X
B
D
X
H
H
H
H
L
L
X
Notes
1
1
2, 3
2, 3
2, 3, 4
2, 3, 4
2, 3, 4
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.01 7/2001
5/23
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
