Preliminary
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
Type
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
In
CK
In
Clock Input Signal
BA
In
Byte Write signal for data inputs DQA1–DQA9; active low
Byte Write signal for data inputs DQB1–DQB9; active low
Byte Write signal for data inputs DQC1–DQC9; active low
Byte Write signal for data inputs DQD1–DQD9; active low
Write Enable; active low
BB
In
BC
In
BD
In
W
In
E1
In
Chip Enable; active low
E2
In
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
E3
In
G
In
ADV
CKE
NC
In
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
In
—
I/O
I/O
I/O
I/O
In
DQA
DQB
DQC
DQD
ZZ
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
LBO
TMS
In
Scan Test Mode Select
Rev: 1.00 9/2004
4/37
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
