GS816236BB-150 参数 Datasheet PDF下载

Preliminary

GS816218/36BB

GS816218/36B BGA Pin Description

Symbol

A

0

, A

1

A

DQ

A

DQ

B

DQ

C

DQ

D

B

A

, B

B

, B

C

, B

D

NC

CK

BW

GW

E

1

G

ADV

ADSP, ADSC

ZZ

FT

LBO

ZQ

SCD

TMS

TDI

TDO

TCK

V

DD

V

SS

V

DDQ

Type

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D

I/Os; active low

No Connect

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

Single Cycle Deselect/Dual Cyle Deselect Mode Control

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.0 9/2004

4/31

© 2004, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.