GS816273C-250 参数 Datasheet PDF下载

GS816273C-250/225

Mode Pin Functions

Mode Name

Burst Order Control

Power Down Control

Single/Dual Cycle Deselect Control

FLXDrive Output Impedance Control

Pin

Name

LBO

ZZ

SCD

ZQ

State

L

H

L or NC

H

L

H or NC

L

H or NC

L

Function

Linear Burst

Interleaved Burst

Active

Standby, I

DD

= I

SB

Dual Cycle Deselect

Single Cycle Deselect

High Drive (Low Impedance)

Low Drive (High Impedance)

Activate DQPx I/Os (x18/x36

mode)

Deactivate DQPx I/Os (x16/x32

mode)

9th Bit Enable

PE

H or NC

Note:

There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the

above tables.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

00

01

10

01

10

11

10

11

00

11

00

01

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

00

01

10

01

00

11

10

11

00

11

10

01

4th address

11

00

01

10

Note:

The burst counter wraps to initial state on the 5th clock.

4th address

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.03 7/2004

4/25

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.