GS8162Z18/36B(B/D)
Synchronous Truth Table
Operation
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Abort, Continue Burst
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle
Deselect Cycle, Continue
Sleep Mode
Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E
1
E
2
E
3
G ZZ
R
B
R
B
W
B
B
D
D
D
D
D
External
Next
External
Next
External
Next
Next
None
None
None
None
None
None
Current
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
L-H
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
H
L
H
L
H
H
L
L
L
L
H
X
X
H
X
H
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
H
X
X
X
H
X
X
X
L
X
L
X
L
X
X
H
X
X
L
X
X
X
H
X
H
X
H
X
X
X
X
L
H
X
X
X
L
X
L
X
L
X
X
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
DQ
Q
Q
High-Z
High-Z
D
D
Notes
1,10
2
1,2,10
3
1,3,10
High-Z 1,2,3,10
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
-
4
1
1
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.04a 2/2006
8/34
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
