GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description
Symbol
A0, A1
An
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
CKE
PE
W
Clock Input Signal; active high
I
Clock Enable; active low
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Write Enable; active low
I
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
ZZ
I
Burst address counter advance enable; active high
Sleep mode control; active high
I
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
I/O and Core Ground
DD
V
I
SS
V
I
Output driver power supply
DDQ
BPR1999.05.18
Rev: 2.21 11/2004
8/38
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
