GS8170DD36C-333/300/250/200
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.
The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter
generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM
by driving the ADV pin low, into Load mode.
SigmaRAM DDR Burst Read with Counter Wrap-around
Read
CK
External
Address
Internal
Address
Continue
Continue
Read
Continue
A2
XX
XX
B0
XX
XX
A2
A3
A0
A1
A2
A3
B0
B1
B2
B3
B1
ADV
Counter Wraps
/E
1
/W
QA2
DQ
QA3
QA0
QA1
QA2
QA3
QB0
QB1
CQ
Rev: 2.03 1/2005
6/29
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
