GS82032AT-180/166/150/133/100/66/4/5/6
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
Pin Name
LBO
FT
ZZ
State
L
H or NC
L
H or NC
L or NC
H
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Note:
There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
1st address
2nd address
3rd address
4th address
Interleaved Burst Sequence
A[1:0]
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.12 10/2004
5/22
© 2000, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
