GS8320E18T-150 参数 Datasheet PDF下载

Preliminary

GS8320E18/32/36T-xxxV

Simplified State Diagram with G

X

Deselect

W

W

X

W

CW

R

R

First Write

R

CR

First Read

X

CR

CW

W

X

Burst Write

R

CR

W

CW

R

X

Burst Read

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.03 6/2006

11/24

© 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.