GS8321E18/32/36E-250/225/200/166/150/133
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
LBO
H
L
Output Register Control
FT
H or NC
L or NC
H
Active
Power Down Control
ZZ
Standby, I = I
DD SB
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.03 4/2005
8/34
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
