Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location
P6
L6
T6
G6, J6
N6
H6, J6, K6, M6
A8, N6
B6
T7
F6
W3
W4
W8
W9
A4, N6
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,
R6, R7
D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,
P4, P5, P7, P8, P9, T3, T9
E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9
Symbol
ZZ
FT
LBO
MCH
MCH
MCL
MCL
W
PE
ZQ
TMS
TDI
TDO
TCK
V
DD
V
DD
V
SS
V
DDQ
Type
I
I
I
I
I
Description
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Must Connect High
Must Connect High (x72 and x36 versions)
Must Connect Low
Must Connect Low (x18 version)
I
I
I
I
I
O
I
I
I
I
I
Write Enable; active low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36
Mode)
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Core power supply (x18 version)
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.00 10/2001
6/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
