GS832018T-133 参数 Datasheet PDF下载

Preliminary

GS832018/32/36T-250/225/200/166/150/133

TQFP Pin Description

Symbol

A

0

, A

1

A

DQ

A

DQ

B1

DQ

C

DQ

D

NC

BW

B

A

, B

B

B

C

, B

D

CK

GW

E

1

, E

3

E

2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

V

DD

V

SS

V

DDQ

Type

I

I

I/O

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Data Input and Output pins

No Connect

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQ

A

, DQ

B

Data I/Os; active low

Byte Write Enable for DQ

C

, DQ

D

Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.02 10/2004

5/25

© 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.