欢迎访问ic37.com |
会员登录 免费注册
发布采购

GS832018T-200 参数 Datasheet PDF下载

GS832018T-200图片预览
型号: GS832018T-200
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×18 , 1M ×32 , 1M ×36 36MB同步突发静态存储器 [2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs]
分类和应用: 存储静态存储器
文件页数/大小: 25 页 / 645 K
品牌: GSI [ GSI TECHNOLOGY ]
 浏览型号GS832018T-200的Datasheet PDF文件第2页浏览型号GS832018T-200的Datasheet PDF文件第3页浏览型号GS832018T-200的Datasheet PDF文件第4页浏览型号GS832018T-200的Datasheet PDF文件第5页浏览型号GS832018T-200的Datasheet PDF文件第6页浏览型号GS832018T-200的Datasheet PDF文件第7页浏览型号GS832018T-200的Datasheet PDF文件第8页浏览型号GS832018T-200的Datasheet PDF文件第9页  
Preliminary
GS832018/32/36T-250/225/200/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832018/32/36T operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS832018/32/36T is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
285
350
6.5
6.5
205
235
265
320
7.0
7.0
195
225
245
295
7.5
7.5
185
210
220 210 185 mA
260 240 215 mA
8.0
8.0
8.5
8.5
8.5
8.5
ns
ns
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
175 165 155 mA
200 190 175 mA
Rev: 1.02 10/2004
1/25
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.