GS840F18/32/36AT-7.5/8/8.5/10/12
TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC standard 100-lead TQFP
• Pb-Free 100-lead TQFP package available
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
7.5 ns – 12 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin
option (pin 14 on TQFP). Board sites for Flow Through Burst
RAMS should be designed with V
SS
connected to the FT pin
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s Pipeline/Flow Through-configurable Burst
RAMS or any vendor’s Flow Through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable Flow Through Burst
RAM, like this RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS840F18/32/36A operates on a 3.3 V power supply and
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Functional Description
Applications
The GS840F18/32/36A is a 4,718,592-bit (4,194,304-bit for
x32 version) high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support. The
GS840F18/32/36A is available in a JEDEC standard 100-lead
TQFP package.
Controls
Addresses, data I/Os, chip enables (E
1
, E
2
, E
3
), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Parameter Synopsis
–7.5
-8
-8.5
-10
-12
Flow
t
KQ
7.5 ns
8 ns
8.5 ns
10 ns
12 ns
Through tCycle 8.5 ns
9 ns
10 ns
12 ns
15 ns
2-1-1-1
I
DD
245 mA 210 mA 190 mA 165 mA 135 mA
Rev: 1.09 10/2004
1/21
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
