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GS8644Z36E-133 参数 Datasheet PDF下载

GS8644Z36E-133图片预览
型号: GS8644Z36E-133
PDF下载: 下载PDF文件 查看货源
内容描述: 72MB流水线和流量通过同步NBT SRAM [72Mb Pipelined and Flow Through Synchronous NBT SRAM]
分类和应用: 存储内存集成电路静态存储器时钟
文件页数/大小: 30 页 / 1434 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary
GS8644Z18/36E-xxxV
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V core power supply and I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb
devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 165-bump BGA package available
72Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8644Z18/36E-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8644Z18/36E-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 165-bump BGA package.
Functional Description
The GS8644Z18/36E-xxxV is a 72Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
t
KQ
tCycle
Curr (x18)
Curr (x36)
3.0
4.0
385
450
6.5
6.5
265
290
3.0
4.4
360
415
6.5
6.5
265
290
3.0
5.0
335
385
6.5
6.5
265
290
3.0
6.0
305
345
8.0
8.0
255
280
3.3
6.7
295
325
8.5
8.5
240
265
3.5
7.5
265
295
8.5
8.5
225
245
ns
ns
mA
mA
ns
ns
mA
mA
Flow
Through
2-1-1-1
Rev: 1.05 6/2006
1/30
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.