Preliminary
GS8662Q08/09/18/36E-300/250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a.
1b.
1c.
Apply V
DD
.
Apply V
DDQ
.
Apply V
REF
(may also be applied at the same time as V
DDQ
).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become
stablized.
DLL Constraints
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t
KCVar
on page 21).
• The DLL cannot operate at a frequency lower than 119 MHz.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
the initial stage.
Power-Up Sequence (Doff controlled)
Power UP Interval
Unstable Clocking Interval
DLL Locking Interval (1024 Cycles)
Normal Operation
K
K
V
DD
V
DDQ
V
REF
Doff
Power-Up Sequence (Doff tied High)
Power UP Interval
Unstable Clocking Interval
Stop Clock Interval
30ns Min
DLL Locking Interval (1024 Cycles)
Normal Operation
K
K
V
DD
V
DDQ
V
REF
Doff
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Rev: 1.01 9/2005
9/35
© 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
