欢迎访问ic37.com |
会员登录 免费注册
发布采购

GS88118BD-200 参数 Datasheet PDF下载

GS88118BD-200图片预览
型号: GS88118BD-200
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×18 , 256K ×32 , 256K ×36 9MB同步突发静态存储器 [512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs]
分类和应用: 存储静态存储器
文件页数/大小: 39 页 / 1692 K
品牌: GSI [ GSI TECHNOLOGY ]
 浏览型号GS88118BD-200的Datasheet PDF文件第2页浏览型号GS88118BD-200的Datasheet PDF文件第3页浏览型号GS88118BD-200的Datasheet PDF文件第4页浏览型号GS88118BD-200的Datasheet PDF文件第5页浏览型号GS88118BD-200的Datasheet PDF文件第6页浏览型号GS88118BD-200的Datasheet PDF文件第7页浏览型号GS88118BD-200的Datasheet PDF文件第8页浏览型号GS88118BD-200的Datasheet PDF文件第9页  
GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
100-pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
333 MHz–150 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
SCD (Single Cycle Deselect) pipelined synchronous SRAM.
DCD (Dual Cycle Deselect) versions are also available. SCD
SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in
the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and 2.5 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) is a
9,437,184-bit high performance synchronous SRAM with a 2-
bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
-333
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5
3.0
250
290
4.5
4.5
200
230
Paramter Synopsis
-300
2.5
3.3
230
265
5.0
5.0
185
210
-250
2.5
4.0
200
230
5.5
5.5
160
185
-200
3.0
5.0
170
195
6.5
6.5
140
160
-150
3.8
6.7
140
160
7.5
7.5
128
145
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.05 11/2005
1/39
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.