GS88237BGB-200 参数 Datasheet PDF下载

GS88237BB/D-333/300/250/200

GS882V37 BGA Pin Description

Symbol

A

0

, A

1

A

DQ

A

DQ

B

DQ

C

DQ

D

B

A

, B

B

, B

C

, B

D

NC

NC

CK

BW

GW

E

1

E

3

E

2

G

ADV

ADSC, ADSP

ZZ

LBO

PE

ZQ

TMS

TDI

TDO

TCK

MCL

SCD

V

DD

V

SS

V

DDQ

Type

I

I

I/O

I

—

—

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I

—

—

I

I

I

Description

Address field LSBs and Address Counter Preset Inputs

Address Inputs

Data Input and Output pins

Byte Write Enable for DQ

A

, DQ

B

, DQ

C

, DQ

D

I/Os; active low

No Connect

No Connect

Clock Input Signal; active high

Byte Write—Writes all enabled bytes; active low

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active l0w

Address Strobe (Processor, Cache Controller); active low

Sleep mode control; active high

Linear Burst Order mode; active low

9th Bit Enable; active low (only on 119-bump BGA)

FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Must Connect Low

Single Cycle Deselect/Dual Cyle Deselect Mode Control

Core power supply

I/O and Core Ground

Output driver power supply

Rev: 1.04 3/2005

4/29

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.