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HDD128M72D18RPW-16B 参数 Datasheet PDF下载

HDD128M72D18RPW-16B图片预览
型号: HDD128M72D18RPW-16B
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM模块1024MByte。点击( 128Mx72bit )的基础上, 64Mx8 , 4Banks , 8K参考, 184PIN -DIMM与PLL和注册 [DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 14 页 / 446 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
Input / Output Capacitance
(V
DD
= min to max, V
DDQ
= 2.5V to 2.7V, T
A
= 25°C, f = 100MHz)
DESCRIPTION
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)
Input capacitance(CKE0,CKE1)
Input capacitance(/CS0)
Input capacitance(CK0~CK2, /CK0~/CK2)
Input capacitance(DM0~DM7)
Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7)
Data input/output capacitance (CB0~CB7)
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
C
OUT2
MIN
9
9
9
11
14
14
14
HDD128M72D18RPW
MAX
11
11
11
12
16
16
16
UNITS
pF
pF
pF
pF
pF
pF
pF
DC Characteristics
(V
DD
= 2.7V, T =10°C)
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
Normal
IDD6
IDD7A
Low
Power
-16B
(DDR333@CL=2.5)
2230
2500
590
1420
950
1040
1690
2540
2630
3130
590
560
4520
-13A
(DDR266@CL=2.0)
2010
2280
540
1290
900
990
1560
2280
2330
2910
540
510
4080
-13B
(DDR266@CL=2.5)
2010
2280
540
1290
900
990
1560
2280
2330
2910
540
510
4080
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Optional
Notes
Notes:
Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC Operating Conditions
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-tion.
the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
STMBOL
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
0.7
0.5*VDDQ-0.2
MIN
VREF + 0.35
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
V
V
V
1
2
MAX
UNIT
NOTE
URL : www.hbe.co.kr
REV 1.0 (January. 2005)
6
HANBit Electronics Co.,Ltd.