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HDD32M64F8K 参数 Datasheet PDF下载

HDD32M64F8K图片预览
型号: HDD32M64F8K
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM模组256Mbyte ( 32Mx64bit ) ,基于on16Mx8,4Banks , 4K参考, SMM , [DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM,]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 11 页 / 160 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HDD32M64F8K
DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks,
4K Ref., SMM,
Part No. HDD32M64F8K
GENERAL DESCRIPTION
The HDD32M64F8K is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module.
The module consists of sixteen CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K
EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed
circuit board in parallel for each DDR SDRAM. The HSD32M64F8K is a SMM(Stackable Memory Module
type) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to
be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
Part Identification
HDD32M64F8K
10A :
HDD32M64F8K
13A :
HDD32M64F8K
13B :
100MHz (CL=2)
133MHz (CL=2)
133MHz (CL=2.5)
256MB(32Mx64) Unbuffered DDR SMM based on 16Mx8 DDR SDRSM
2.5V
±
0.2V VDD and VDDQ power supply
Auto & self refresh capability (4096 Cycles/64ms)
All input and output are compatible with SSTL_2 interface
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
The used device is 4M x 8bit x 4Banks DDR SDRAM
URL : www.hbe.co.kr
REV 1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.