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HDD32M64F8-13B 参数 Datasheet PDF下载

HDD32M64F8-13B图片预览
型号: HDD32M64F8-13B
PDF下载: 下载PDF文件 查看货源
内容描述: DDR SDRAM模组256Mbyte ( 32Mx64bit )的基础上, 32Mx8 , 4Banks , 8K参考, SMM , [DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM,]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 11 页 / 197 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HDD32M64F8
DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks,
8K Ref., SMM,
Part No. HDD32M64F8
GENERAL DESCRIPTION
The HANBiT HDD32M64F8 is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT
HDD32M64F8 consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The HDD32M64F8 is Dual In-line Memory Modules and inten-ded for mounting into
200pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be
useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
Part Identification
HDD32M64F8
10A : 100MHz (CL=2)
HDD32M64F8
13A : 133MHz (CL=2)
HDD32M64F8
13B : 133MHz (CL=2.5)
Power supply : V
DD
: 2.5V
±
0.2V, V
DDQ
: 2.5V
±
0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
URL : www.hbe.co.kr
REV 2.0 (November.2002)
1
HANBit Electronics Co.,Ltd.