HANBit
CS# >= VIH(min), CKE>=VIH(min)
one
bank
active, active
–
precharge,
tRC=tRASmax
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B, DQ, DQS and DM inputs changing
twice per clock cycle Address and other control
inputs changing once per clock cycle
BL = 2, reads, continuous burst
One bank open, Address and control inputs
changing once per clock cycle, I
OUT
= 0mA
BL = 2, write, continuous burst
One bank open, Address and control inputs
changing once per clock cycle
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz,
distributed refresh
CKE =< 0.2V, External clock should be on
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
Four bank interleaving with BL=4
-Refer to the following page for detailed test
condition
HDD64M72D18W
Active standby
I
DD3N
current
1053
900
900
mA
Operating current
(burst read)
I
DD4R
1620
1845
1845
mA
Operating current
(Bust write)
I
DD4W
1485
1755
1755
mA
mA
Auto refresh current
I
DD5
1845
2070
2070
Self
refresh
current
Normal
I
DD6
Low Power
I
DD7A
54
27
2790
54
27
3015
54
27
3015
mA
Operating current
(Four bank operation)
mA
Notes:
Operation at above absolute maximum rating can adversely affect device reliability
AC OPERATING CONDITIONS
PARAMETER
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
STMBOL
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
MIN
VREF + 0.31
MAX
UNIT
NOTE
3
VREF - 0.31
V
V
V
3
1
2
0.7
0.5*VDDQ-0.2
VDDQ+0.6
0.5*VDDQ+0.2
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V
IX
is expected to equal 0.5* V
DDQ
of the transmitting device and must track variations in the DC level of
the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the
pad in simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited
20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(V
IH
/V
IL
)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
URL : www.hbe.co.kr
REV 1.0 (August.2002)
7
VALUE
0.5 * V
DDQ
1.5
1.0
V
REF
+0.35/V
REF
V
REF
V
TT
See Load Circuit
UNIT
V
V
V
V
V
V
V
NOTE
HANBit Electronics Co.,Ltd
.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
