HANBit
HFDOM40P-xxxSx
3. INTERFACE BUS TIMING
ACCESS SPCIFICATIONS
IDE MODE I/O ACCESS SPECIFICATIONS
In this True IDE Mode the Flash Disk Module protocol and configuration are disabled and only I/O operations to the
Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host.
Table 3.1 IDE Mode I/O Access Mode
Mode
-CE2 -CE1
A2-A0
x
-IORD -IOWR
D15 - D8
High Z
D7 – D0
High Z
Invalid Mode
L
H
H
H
H
H
L
L
H
L
x
x
x
x
Standby Mode
x
High Z
High Z
Task File Write
1-7h
1-7h
0
H
L
L
Don’t Care
High Z
Data In
Task File Read
L
H
L
Data Out
Even Byte in
Even Byte out
Control In
Status Out
Data Register Write
Data Register Read
Control Register Write
All Status Read
L
H
L
Odd Byte in
Odd Byte out
Don’t Care
High Z
L
0
H
L
H
H
6h
H
L
L
6h
H
Table 3.2 IDE Mode I/O Read Timing
Min. ns
Max. ns
Parameter
Data Delay after IORD
Symbol
IEEE Symbol
tlGLQV
td (IORD)
100
Data Hold following IORD
IORD Width Time
th (IORD)
tlGHQX
tlGLIGH
tAVIGL
tlGHAX
tELIGL
tlGHEH
tAVISL
tAVISH
0
165
70
20
5
tw (IORD)
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
tsuA (IORD)
thA (IORD)
tsuCE (IORD)
thCE (IORD)
tdfIOIS16 (ADR)
tdrIOIS16 (ADR)
CE Hold following IORD
20
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
35
35
NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time
from
–WAIT high to -IORD high is 0nsec, but minimum -IORD width must still be met.
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REV 1.0 (August.2002)
8 / 10
HANBit Electronics Co., Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
