HANBit
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
Block Erase Time
Chip Erase Time
Word Programming Time
Chip Programming Time
-
-
-
TYP.
0.7
27
11
12
330
36
MAX.
15
sec
sec
µs
sec
UNIT
HMF1M32F2VSA
COMMENTS
Excludes 00H programming
prior to erasure
Excludes system-level
overhead
TSOP CAPACITANCE
PARAMETER
SYMBOL
C
IN
C
OUT
C
IN2
PARAMETER
DESCRIPTION
Input Capacitance
Output Capacitance
Control Pin Capacitance
TEST SETUP
V
IN
= 0
V
OUT
= 0
V
IN
= 0
MIN
-
-
-
MAX
10
10
10
UNIT
pF
pF
pF
Notes
: Capacitance is periodically sampled and not 100% tested.
TEST SPECIFICATIONS
TEST CONDITION
Output load
Input rise and full times
Input pulse levels
Input timing measurement reference levels
Output timing measurement reference levels
VALUE
1TTL gate
5
0 to 3
1.5
1.5
ns
V
V
V
UNIT
5.0V
2.7kΩ
Device
Under
Test
C
L
IN3064
or Equivalent
6.2kΩ
Diodes = IN3064
or Equivalent
Note
: C
L
= 100pF including jig capacitance
URL :
www.hbe.co.kr
REV.02(August, 2002)
4
HANBit Electronics Co., Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
