HANBit
2. Icc active while embedded algorithm (program or erase) is in progress
3. Maximum Icc current specifications are tested with Vcc=Vcc max
HMF4M32M8V
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
MIN.
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time
-
-
-
TYP.
0.7
25
9
12
300
36
MAX.
15
sec
sec
µs
sec
Excludes system-level
overhead
Excludes 00H programming
prior to erasure
UNIT
COMMENTS
TSOP CAPACITANCE
PARAMETER
SYMBOL
C
IN
C
OUT
C
IN2
PARAMETER
DESCRIPTION
Input Capacitance
Output Capacitance
Control Pin Capacitance
o
TEST SETUP
V
IN
= 0
V
OUT
= 0
V
IN
= 0
TYP.
6
8.5
7.5
MAX
7.5
12
9
UNIT
pF
pF
pF
Notes
: Test conditions T
A
= 25 C, f=1.0 MHz.
AC CHARACTERISTICS
u
Read Only Operations Characteristics
PARAMETER
SYMBOLS
DESCRIPTION
JEDEC STANDARD
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
QH
Read Cycle Time
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
/CE = V
IL
/OE = V
IL
/OE = V
IL
Min
Max
Max
Max
Max
Max
Min
TEST SETUP
-70R
70
70
70
30
25
25
-80
80
80
80
30
25
25
0
-90
90
90
90
35
30
30
-120
120
120
120
50
30
30
ns
ns
ns
ns
ns
ns
ns
Speed Options
UNIT
TEST SPECIFICATIONS
TEST CONDITION
Output load
Output load capacitance,C
L
(Including jig capacitance)
Input rise and fall times
Input pulse levels
Input timing measurement reference levels
Output timing measurement reference levels
URL:www.hbe.co.kr
REV.02(August,2002).
70R, 80
1TTL gate
30
5
0.0-3.0
1.5
1.5
90, 120
UNIT
100
pF
ns
V
V
V
4
HANBit Electronics Co., Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
