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HMF4M32M8VGL-70 参数 Datasheet PDF下载

HMF4M32M8VGL-70图片预览
型号: HMF4M32M8VGL-70
PDF下载: 下载PDF文件 查看货源
内容描述: 闪存ROM模块16兆字节( 4Mx32Bit ) , 72PIN - SIMM , 3.3V设计 [Flash-ROM Module 16MByte (4Mx32Bit), 72Pin-SIMM, 3.3V Design]
分类和应用: 闪存
文件页数/大小: 11 页 / 428 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
 浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第1页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第2页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第3页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第5页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第6页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第7页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第8页浏览型号HMF4M32M8VGL-70的Datasheet PDF文件第9页  
HANBit  
HMF4M32M8VGL  
3. Maximum Icc current specifications are tested with Vcc=Vcc max  
ERASE AND PROGRAMMING PERFORMANCE  
LIMITS  
PARAMETER  
UNIT  
COMMENTS  
MIN.  
TYP.  
0.7  
25  
MAX.  
Sector Erase Time  
Chip Erase Time  
-
15  
sec  
sec  
ms  
Excludes 00H programming  
prior to erasure  
Byte Programming Time  
Chip Programming Time  
-
-
9
300  
36  
Excludes system-level  
overhead  
12  
sec  
TSOP CAPACITANCE  
PARAMETER  
SYMBOL  
PARAMETER  
DESCRIPTION  
TEST SETUP  
TYP.  
MAX  
UNIT  
CIN  
COUT  
CIN2  
Input Capacitance  
VIN = 0  
VOUT = 0  
VIN = 0  
6
7.5  
12  
9
pF  
pF  
pF  
Output Capacitance  
8.5  
7.5  
Control Pin Capacitance  
: Test conditions TA = 25o C, f=1.0 MHz.  
Notes  
AC CHARACTERISTICS  
Read Only Operations Characteristics  
u
PARAMETER  
SYMBOLS  
Speed Options  
DESCRIPTION  
TEST SETUP  
UNIT  
JEDEC STANDARD  
-70R  
-80  
-90  
-120  
tAVAV  
tAVQV  
tELQV  
tGLQV  
tEHQZ  
tGHQZ  
tAXQX  
tRC  
tACC  
tCE  
tOE  
tDF  
Read Cycle Time  
Min  
Max  
Max  
Max  
Max  
Max  
Min  
70  
70  
70  
30  
25  
25  
80  
80  
80  
30  
25  
25  
90  
90  
90  
35  
30  
30  
120  
120  
120  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
/CE = VIL  
/OE = VIL  
Address to Output Delay  
Chip Enable to Output Delay  
Output Enable to Output Delay  
Chip Enable to Output High-Z  
/OE = VIL  
30  
tDF  
Output Enable to Output High-Z  
Output Hold Time From Addresses,  
/CE or /OE, Whichever Occurs First  
30  
tQH  
0
TEST SPECIFICATIONS  
TEST CONDITION  
70R, 80  
90, 120  
UNIT  
Output load  
1TTL gate  
Output load capacitance,CL (Including jig capacitance)  
Input rise and fall times  
30  
100  
pF  
ns  
V
5
Input pulse levels  
0.0-3.0  
4
URL: www.hbe.co.kr  
REV.02(August,2002)  
HANBit Electronics Co., Ltd.