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HMN1M8DV-85I 参数 Datasheet PDF下载

HMN1M8DV-85I图片预览
型号: HMN1M8DV-85I
PDF下载: 下载PDF文件 查看货源
内容描述: 非易失性SRAM模块8Mbit的( 1024K X 8位) 36PIN DIP, 3.3V [Non-Volatile SRAM MODULE 8Mbit (1024k x 8bit) 36Pin-DIP, 3.3V]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 199 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HMN1M8DV  
READ CYCLE (TA= TOPR, VCCmin VCCVCCmax  
)
-70  
-85  
-120  
-150  
PARAMETER  
SYMBOL  
CONDITIONS  
UNIT  
MIN MAX MIN MAX MIN MAX MIN MAX  
Read Cycle Time  
tRC  
tACC  
tACE  
tOE  
70  
-
-
85  
-
-
120  
-
-
120  
120  
60  
-
150  
-
-
150  
150  
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Output load A  
Output load A  
Output load A  
Output load B  
Output load B  
Output load B  
Output load B  
Output load A  
70  
70  
35  
-
85  
85  
45  
-
Chip enable access time  
-
-
-
-
Output enable to Output valid  
Chip enable to output in low Z  
Output enable to output in low Z  
Chip disable to output in high Z  
Output disable to output high Z  
Output hold from address change  
-
-
-
-
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
5
5
0
0
10  
5
0
0
0
10  
5
10  
5
-
-
0
-
-
25  
25  
-
35  
25  
-
0
45  
35  
-
0
60  
50  
-
0
0
10  
10  
WRITE CYCLE (TA= TOPR, Vccmin Vcc Vccmax  
)
-70  
-85  
-120  
-150  
UNI  
PARAMETER  
SYMBOL CONDITIONS  
T
MIN MAX MIN MAX MIN MAX  
Min  
Max  
Write Cycle Time  
Chip enable to end of write  
Address setup time  
tWC  
70  
65  
0
-
-
85  
75  
0
-
-
120  
100  
0
-
-
150  
100  
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCW  
tAS  
Note 1  
Note 2  
Note 1  
Note 1  
Note 3  
Note 3  
-
-
-
-
Address valid to end of write  
Write pulse width  
tAW  
65  
55  
5
-
75  
65  
5
-
100  
85  
5
-
90  
90  
5
-
tWP  
tWR1  
tWR2  
tDW  
tDH1  
tDH2  
tWZ  
-
-
-
-
Write recovery time (write cycle 1)  
Write recovery time (write cycle 2)  
Data valid to end of write  
-
-
-
-
15  
30  
0
-
15  
35  
0
-
15  
45  
0
-
15  
50  
0
-
-
-
-
-
Data hold time (write cycle 1)  
Data hold time (write cycle 2)  
Write enabled to output in high Z  
Output active from end of write  
Note 4  
Note 4  
Note 5  
Note 5  
-
-
-
-
10  
0
-
10  
0
-
10  
0
-
0
-
25  
-
30  
-
40  
-
0
50  
-
tOW  
5
0
0
5
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.  
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE  
going low and /WE going low.  
3. Either tWR1 or tWR2 must be met.  
4. Either tDH1 or tDH2 must be met.  
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-  
impedance state.  
5
URL:www.hbe.co.kr  
Rev.0.0 (FEBRUARY/ 2002)  
HANBit Electronics Co.,Ltd