HANBit
POWER-DOWN/POWER-UP CYCLE
(T
A
= T
OPR,
V
CC
=5V)
PARAMETER
V
CC
slew, 4.75 to 4.25V
V
CC
slew, 4.75 to V
SO
V
CC
slew, V
SO
to V
PFD
(max)
Chip enable recovery time
Data-retention time in
Absence of V
CC
Data-retention time in
Absence of V
CC
Write-protect time
SYMBOL
t
PF
t
FS
t
PU
Time during which SRAM
t
CER
is write-protected after V
CC
passes V
PFD
on power-up.
t
DR
t
DR-N
T
A
= 25℃
T
A
= 25℃ ; industrial
temperature range (-N) only
Delay after V
CC
slews down
t
WPT
past V
PFD
before SRAM is
Write-protected.
40
100
10
6
-
-
40
80
CONDITIONS
MIN
300
10
0
TYP.
-
-
-
HMN328D
MAX
-
-
-
UNIT
㎲
㎲
㎲
120
ms
-
-
years
years
150
㎲
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*
1,2
t
RC
Address
t
ACC
t
OH
D
OUT
Previous Data Valid
Data Valid
- READ CYCLE NO.2 (/CE Access)
*1,3,4
/CE
t
ACE
t
CLZ
D
OUT
High-Z
t
RC
t
CHZ
High-Z
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
6
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
