HANBit
DATA RETENTION CHARACTERISTICS
(T
A
= T
OPR,
V
CC
=5V)
PARAMETER
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
SYMBOL
V
DR
I
DR
t
SDR
t
RDR
CONDITIONS
CE≥
Vcc-0.2V
Vcc=3.0V, CE≥
Vcc
See data retention waveform
0
5
MIN
2.0
TYP.
-
-
-
-
HMN4M8D
MAX
5.5
20
-
UNIT
V
uA
ms
-
POWER-DOWN/POWER-UP CYCLE
(T
A
= T
OPR,
V
CC
=5V)
PARAMETER
V
CC
slew, 4.75 to 4.25V
V
CC
slew, 4.75 to V
SO
V
CC
slew, V
SO
to V
PFD
(max)
SYMBOL
t
PF
t
FS
t
PU
Time during which SRAM
is write-protected after V
CC
passes V
PFD
on power-up.
T
A
= 25℃
Delay after Vcc slews down
past V
PFD
before SRAM is
Write-protected.
CONDITIONS
MIN
300
10
0
TYP.
-
-
-
MAX
-
-
-
UNIT
㎲
㎲
㎲
Chip enable recovery time
Data-retention time in
Absence of V
CC
t
CER
40
80
120
ms
t
DR
5
-
-
years
Write-protect time
t
WPT
40
100
150
㎲
TIMING WAVEFORM
- Read Cycle No.1 (Address Access)*
1,2
t
RC
Address
t
ACC
t
OH
D
OUT
Previous Data Valid
Data Valid
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
6
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
