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HMNR1288DV-70 参数 Datasheet PDF下载

HMNR1288DV-70图片预览
型号: HMNR1288DV-70
PDF下载: 下载PDF文件 查看货源
内容描述: 5.0或3.3V , 1兆位( 128千位×8 ) TIMEKEEPER NVSRAM [5.0 or 3.3V, 1 Mbit (128 Kbit x 8) TIMEKEEPER NVSRAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 14 页 / 315 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HMNR1288D(V)
FUNCTIONAL DESCRIPTION
The HMNR1288D(V) is a full function, year 2000 compliant (Y2KC), real
time clock/calendar (RTC) and 128K x 8 non-
volatile static RAM. User access to all registers within the HMNR1288D(V) is accomplished with a bytewide interface . The
Real-time clock (RTC) information and control bits reside in the eight upper most RAM locations. The RTC registers
contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date
of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double b uffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The HMNR1288D(V) also contains its own
power-fail circuitry which deselects the device when the V
CC
supply is in an out of tolerance condition. This feature
prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and update cycles are
avoided.
BLOCK DIAGRAM
OSCILLATOR AND
CLOCK CHAIN
32.768KHz
CRYSTAL
POWER
16 x 8
TIMEKEEPER
REGISTER
/RST
IRQ/FT
A0 ~ A16
LITHIUM
CELL
V
PFD
VOLTAGE SENSE
AND
SWITCHING
CIRCURITY
131,056 x 8
SRAM ARRAY
DQ0 ~ DQ7
/CE
/WE
/OE
Vcc
A0-A16 : Address Input
/CE : Chip Enable
V
ss
: Ground
DQ0-DQ7 : Data In / Data Out
/RST : Reset Output (Open Drain)
/WE : Write Enable
/OE : Output Enable
V
CC
: Power (+5V or +3.3V)
NC : No Connection
Vss
IRQ/FT : Interrupt/Frequency Test Output (Open Drain)
URL : www.hbe.co.kr
Rev. 1.0 (April, 2002)
2
HANBit Electronics Co.,Ltd