HANBit
OPERATING MODES
HMNR5128D(V)
The 32-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single
package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte
7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock
calibration setting. The seven clock bytes (7FFFFh-7FFF9h) are not the actual clock counters, they are memory locations
consisting of READ/WRITE memory cells within the static RAM array. The HMNR5128D(V) includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be accessed by the user in
the same manner as any other location in the static memory array. The HMNR5128D(V) also has its own Power-Fail
Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security
in the midst of unpredictable system operation. As V
CC
falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
VCC
4.5V to 5.5V
or
3.0V to 3.6V
V
SO
to V
PFD
(min)
≤
V
SO
(1)
/CE
VIH
VIL
VIL
VIL
X
X
/OE
X
X
VIL
VIH
X
X
/WE
X
VIL
VIH
VIH
X
X
DQ7
–
DQ0
High-Z
DIN
DOUT
High
High
High
Power
Standby
Active
Active
Active
CMOS
Standby
Battery Back-
up
Note : X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
READ Mode
The HMNR5128D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The
unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid
data will be available at the Data I/O pins within Address Access Time (t
AVQV
) after the last address input signal is stable,
providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be
available after the latter of the Chip Enable Access Times (t
ELQV
) or Output Enable Access Time (t
GLQV
). The state of the
eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before t
AVQV
, the data lines will
be driven to an indeterminate state until t
AVQV
. If the Address Inputs are changed while /CE and /OE remain active, output
data will remain valid for Output Data Hold Time (t
AXQX
) but will go indeterminate until the next Address Access.
URL : www.hbe.co.kr
Rev. 2.0 (March, 2002)
5
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
