HANBit
HMS12832M4
( /CE Controlled )
tRC
TIMING WAVEFORM OF READ CYCLE
Address
/CE
tHZ(3,4,5)
tAA
tCO
tLZ(4,5)
tOHZ
tOE
/OE
tOH
tOLZ
High-Z
Data Out
Data Valid
tPD
tPU
50%
lCC
lSB
Vcc Supply
Current
50%
(Read Cycle)
Notes
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
(/OE=Clock )
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
/OE
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ(6)
tOW
Data Out
High-Z
6
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
