HANBit
Notes
(Write Cycle)
HMS1M32M8G/Z8
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the later of /CE going low to the end of write.
4. t
AS
is measured from the address valid to the beginning of wirte.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. D
OUT
is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
H
L
L
L
/WE
X*
H
H
L
/OE
X
H
L
X
MODE
Not Select
Output Disable
Read
Write
I/O PIN
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
Note: X means Don't Care
7
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