欢迎访问ic37.com |
会员登录 免费注册
发布采购

HMS25632Z8B-20 参数 Datasheet PDF下载

HMS25632Z8B-20图片预览
型号: HMS25632Z8B-20
PDF下载: 下载PDF文件 查看货源
内容描述: SRAM模块1M字节( 256K ×32位) , 72引脚 [SRAM MODULE 1Mbyte (256K x 32-Bit) , 72-Pin]
分类和应用: 存储静态存储器
文件页数/大小: 9 页 / 233 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
 浏览型号HMS25632Z8B-20的Datasheet PDF文件第1页浏览型号HMS25632Z8B-20的Datasheet PDF文件第2页浏览型号HMS25632Z8B-20的Datasheet PDF文件第3页浏览型号HMS25632Z8B-20的Datasheet PDF文件第4页浏览型号HMS25632Z8B-20的Datasheet PDF文件第5页浏览型号HMS25632Z8B-20的Datasheet PDF文件第7页浏览型号HMS25632Z8B-20的Datasheet PDF文件第8页浏览型号HMS25632Z8B-20的Datasheet PDF文件第9页  
HANBit
TIMING WAVEFORM OF READ CYCLE
( /CE Controlled )
t
RC
Address
t
AA
/CE
t
LZ(4,5
)
/OE
t
OLZ
Data Out
Vcc Supply
Current
High-Z
Data Valid
HMS25632M8B/Z8B
t
HZ(3,4,5)
t
CO
t
OHZ
t
OE
t
OH
l
CC
l
SB
t
PU
50%
t
PD
50%
Notes
(Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(max.) is less than t
LZ
(min.) both for a given device and from device to device.
5. Transition is measured
±
200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with /CE = V
IL
.
7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE
(/OE = Clock )
t
WC
Address
t
AW
t
WR(5)
/OE
t
CW(3)
/CE
t
AS(4)
t
WP(2)
/WE
t
DW
t
DH
Data Valid
t
OHZ(6)
High-Z
Data In
Data Out
High-Z
6
HANBit Electronics Co.,Ltd.