HANBit
HSD128M72B9K
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, t
RDL
=1CLK and t
DAL
=1CLK+20ns is also supported .
(Recommand : t
RDL
=2CLK and t
DAL
=2CLK & 20ns.)
SYMBOL
t
RRD
(min)
t
RP
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
tRC
(min)
VERSION
-13
15
20
20
45
-12
16
20
20
48
100
65
68
2
2 CLK + t
RP
1
1
1
2
-
1
70
70
-10
20
20
20
50
-10L
20
20
20
50
UNIT
ns
ns
ns
ns
ns
ns
CLK
-
CLK
CLK
CLK
ea
NOTE
1
1
1
1
1
2.5
5
2
2
3
4
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
PARAMETER
CAS
CLK cycle time
latency=3
CAS
latency=2
CAS
CLK to valid
output delay
Output data
hold time
latency=3
CAS
latency=2
CAS
latency=3
t
OH
2.7
t
SAC
-
3
-
3
6
3
7
ns
2
t
CC
-
5.4
SYMBOL
-13
MIN
7.5
1000
-
6
MAX
MIN
8
1000
10
6
-12
MAX
MIN
10
1000
12
6
ns
1,2
-10
MAX
MIN
10
1000
ns
1
-10L
MAX
UNIT
NOTE
URL :
www.hbe.co.kr
REV.0.0(January. 2003)
7
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
