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HSD16M64F8K 参数 Datasheet PDF下载

HSD16M64F8K图片预览
型号: HSD16M64F8K
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组128Mbyte ( 16Mx64bit ) , SMM , 16Mx8 , 4Banks , 4K参考。 3.3V [Synchronous DRAM Module 128Mbyte (16Mx64bit), SMM ,16Mx8, 4Banks, 4K Ref. 3.3V]
分类和应用: 动态存储器
文件页数/大小: 30 页 / 1560 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HSD16M64F8K
Synchronous DRAM Module 128Mbyte (16Mx64bit), SMM ,16Mx8,
4Banks, 4K Ref. 3.3V
Part No. HSD16M64F8K
GENERAL DESCRIPTION
The HSD16M64F8K is a 16M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists
of
eight
CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin
TSSOP package on a 120-pin glass-epoxy. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The HSD16M64F8K is a SMM(Stackable Memory Module type) .Synchronous design allows
precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high
performance memory system applications All module components may be powered from a single 3.3V DC power supply
and all inputs and outputs are LVTTL-compatible.
FEATURES
Part Identification
HSD16M64F8K : 100MHz (CL=2
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±0.3V
power supply
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
The used device is 4M x 8bit x 4Banks SDRAM
& CL=3)
URL:www.hbe.co.kr
REV.1.0(August.2002)
-1
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HANBit Electronics Co.,Ltd.