HANBit
CKE
≥
V
IH
(min)
I
CC2
NS
CLK
≤
V
IL
(max), t
CC
=∞
Input signals are stable
I
CC3
P
Active standby current in
power-down mode
I
CC3
PS
CKE
≤
V
IL
(max), t
CC
=10ns
CKE&CLK
≤
V
IL
(max)
t
CC
=∞
CKE≥V
IH
(min),
CS*≥V
IH
(min), t
CC
=10ns
I
CC3
N
Active standby current in
non power-down mode
(One bank active)
I
CC3
NS
Input signals are changed one
time during 20ns
CKE≥VIH(min)
CLK
≤VIL(max),
t
CC
=∞
Input signals are stable
I
O
= 0 mA
Operating current
I
CC4
(Burst mode)
4Banks Activated
t
CCD
= 2CLKs
Refresh current
Self refresh current
I
CC5
I
CC6
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
Page burst
180
360
36
108
HSD16M72D18A
mA
36
mA
1980 1980 1710 1350 1350
mA
1
1350 1350 1350 1350 1260
mA
mA
mA
2
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V
±
0.3V, TA = 0 to 70° C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
Ns
V
URL: www.hbe.co.kr
REV 1.0 (August.2002)
6
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
