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HSD32M64D16H 参数 Datasheet PDF下载

HSD32M64D16H图片预览
型号: HSD32M64D16H
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组256Mbyte ( 32Mx64bit ) , DIMM基于16Mx8 , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 256Mbyte (32Mx64bit), DIMM based on 16Mx8, 4Banks, 4K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 10 页 / 161 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
CAS latency=2
-
SYMBOL
-13
t
RRD
(min)
t
RP
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
tRC
(min)
HSD32M64D16H
UNIT
-10
20
20
20
50
100
65
70
2
2 CLK + 20 ns
1
1
1
2
ea
1
70
-10L
20
20
20
50
ns
ns
ns
ns
ns
ns
CLK
-
CLK
CLK
CLK
15
20
20
45
NOTE
1
1
1
1
1
2
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
2
2
3
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
.5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
-13
PARAMETER
CLK cycle time
CAS
7.5
latency=3
t
CC
CAS
-
latency=2
CLK to valid
output delay
CAS
5.4
latency=3
t
SAC
CAS
-
latency=2
Output data
hold time
CAS
2.7
latency=3
t
OH
CAS
-
latency=2
URL:www.hbe.co.kr
REV.1.0(August.2002)
-10
MAX
MIN
10
1000
10
1000
12
MAX
MIN
10
-10L
UNIT
NOTE
MAX
SYMBOL
MIN
1000
ns
1
6
6
ns
1,2
6
7
3
3
ns
2
3
3
HANBit Electronics Co.,Ltd.
-7-