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HSD32M64D8KP-13 参数 Datasheet PDF下载

HSD32M64D8KP-13图片预览
型号: HSD32M64D8KP-13
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组256Mbyte ( 32Mx64bit ) ,无缓冲DIMM与基于堆栈16Mx8 , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on Stacked 16Mx8, 4Banks, 4K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 29 页 / 813 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HSD32M64D8KP
Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on
Stacked 16Mx8, 4Banks, 4K Ref., 3.3V
Part No. HSD32M64D8KP
GENERAL DESCRIPTION
The HSD32M64D8KP is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists
of sixteen CMOS 16M x 8 bit(stacking chip) with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin
glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each
SDRAM. The HSD32M64D8KP is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be
useful for a variety of high bandwidth, high performance memory system applications All module components may be
powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
Part Identification
HSD32M64D8KP
10L
HSD32M64D8KP
13
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±0.3V
power supply
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
The used device is 4M x 8bit x 4Banks SDRAM
: 100MHz ( CL=3)
: 133MHz ( CL=3)
URL:www.hbe.co.kr
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HANBiT Electronics Co., Ltd